(a) Field of the Invention
The present invention of power efficient FHSS (Frequency Hopping Spreading Spectrum) base-band hardware architecture with sleep mode can perform a higher system-wide calculation in lower power consumption, provide a precise synchronization of system clock to reduce jitter variance of FHSS system less than three clocks of highest system clock and extend communication range under same RF (Radio Frequency) condition of transmission power and receiving sensitivity.
This invention comprises a digital wireless transceiver device, a bi-directional data interface, a clock recovery circuit, a correlator, a MCU (Micro Control Unit), a coder, a timing_event controller, a series-parallel data converter, a DMA (Direct Memory Access) block, a transceiver controller and an oscillation circuit. The clock recovery circuit connecting to the bi-directional data interface extracts frequency and phase being carried within received data, thereby utilizing the recovered clock to latches received data in secure phase locally. The correlator calculates similarity between shifted-in received data from peer and a pre-configured local access address. An Access_Sync signal is generated when the matching-level of similar pattern exceeds preset condition and then is passed to both the MCU as an interruption signal and to the timing_event controller to record timing as a reference of adjustment. A RX_TRIG (receiving-triggered) signal is also generated to notify the series-parallel data converter to launch bulk data collection. The MCU handles data movement around DMA RAM and FHSS function related block in a specific procedure. At receive mode, the timing_event controller receives the Access_Sync interruption signal from the correlator, and the circuit of system clock captures timing information at the moment of interruption as a reference to adjusts local timing to lock with that of entire wireless digital network. At transmission mode, the timing_event controller generates a TX_TRIG signal to notify the series-parallel data converter to launch bulk data transmission. After the series-parallel data converter being activated, it monitors the status of data buffer progress with preset condition and generates a Wake_Int and a Wrap_Int interruption signals. The DMA circuit includes a DMA arbitrator and a RAM block to coordinate data access from both MCU and series-parallel data converter. The coder circuit can perform FEC (Forward Error Correction), CRC (Cyclic Redundant Check) or scramble functions for both receiving and transmitting data optionally. Accordingly, by adopting the invention architecture of the combination of MCU with dedicated function and specific concurrent operation, hardware circuits can utilize relative much lower system clock to provide same functions only provided by a MCU with higher system clock of the prior art. Thereby, by highly integrating with automatic circuit in charge of massive computation duty for FHSS communication in parallel mode, this invention can extend operation time for a portable FHSS system, and allow system to implement voice or image DSP (Digital Signal Processing) function with a low cost MCU, for instance, an 8-bit MCU.
(b) Description of the Prior Art
The prior art related to MCU or DSP of digital wireless communication system tends to drive system operation with function-oriented software. By following the instructions of MCU, the system executes tasks including access code capturing by shifting and analyzing data bit by bit, local system timing synchronization by reading out reference timing of access code received inside interruption routine, high-MIPS algorithm calculation in generic instruction, and series-to-parallel data transmission and collection handing by a every 8-bit interruption routine of series-parallel interface. Comparing to the invention, prior MCU has to utilize system clock with relatively much higher frequency or to keep in burst working states frequently to provide the same level service and functionality. Moreover, a larger scale jitter and less precise local timing is expected because of variant latency of Access_Sync interruption signal driven from complicated MCU interrupt scheduling and possible variant instruction cycle and decision inside interruption routine. The larger scale jitter forces FHSS receiver using a wider valid frame to verify incoming access code. Therefore, it increases the possibility to get faulty access code to degrade synchronization with central wireless network timing, and corrupts the integrity of receiving data. In the worst case, a reliable data link can be broken, and local FHSS system has to rebuild data link from scratch. Finally, the system stability and effective capability of transmission get downgraded, and more power is consumed to finish a same job. Hence, the new invention focuses on power saving and improvement of communication quality for portable speech equipment.
In an actual application, most of 2.4 GHz ISM band Bluetooth transceiver is using 12 MHz as base system clock before PLL (Phase Lock Loop) upgrade it to higher frequency of clock. If the baseband circuit and the digital signal transceiver can share the same clock source of oscillation, then power consumption of the entire system is optimized. However, a MCU operated at 12 MHz is evidently with insufficient computation power, because most base-band for Bluetooth application are still limited to application of small scale system with low transmission capacity, for instance, joy stick, single channel wireless headset and low-rate wireless serial line, and so on. However, the other high-end applications, like multiple channels of audio and video processing, or extra discrete signal processing capability for voice compression and tone detection, have to utilize more proprietary solution in high cost DSP chips. In short, the prior art have to be modified to meet users' requirements in higher level practical use.